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NASA has selected SiFive, a US chip startup that designs RISC-V CPUs, to provide the “core CPU” for the space agency’s forthcoming High-Performance Spaceflight Computing (HPSC) processor. 

NASA announced in June that its HPSC project would develop new flight-computing technology that will feature “at least 100 times” the computational capacity of current spaceflight computers, which were developed almost 30 years ago. 

These CPUs need to be resistant to radiation damage, operate with minimal power, and turn off when not needed, yet still be capable of robotically landing spacecraft on Mars and supporting astronauts in space. 

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The chief problem with older spaceflight computers is that they’re over-designed, built for the most computational-intensive parts of a mission, such as during a landing sequence on Mars. They also need to operate with minimal electrical power supplies.    

Engineers from NASA’s Jet Propulsion Laboratory (JPL) are leading the HPSC development to deliver multicore chips and its operating software. The HPSC must process data 100 times faster than existing ‘space qualified’ computers because of power constraints. 

According to SiFive, NASA’s HPSC will use an 8-core, SiFive ‘Intelligence’ X280 RISC-V vector core, and four additional SiFive RISC-V cores. 

The chip designer says the X280 has demonstrated the 100-times speed increase required for NASA’s HSPC and is good for applications requiring high throughput, single-thread performance under power constraints. 

“The X280 demonstrates orders of magnitude performance gains over competing processor technology and our SiFive RISC-V IP allows NASA to take advantage of the support, flexibility, and long-term viability of the fast-growing global RISC-V ecosystem,” said Jack Kang, SVP of business development at SiFive.

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NASA’s selection of SiFive is a small but important win for the open-source RISC-V (pronounced “risk-five”) standard, which was invented by University of California Berkeley professors David Patterson and Krste Asanovic╠ü 12 years ago. 

Developers are free to change a RISC-V chip’s instruction set architecture (ISA), which defines how the chip hardware operates. This makes it different to the closed ISAs of Intel’s x86, which dominates PCs and servers, and ARM instructions licensed by ARM Ltd to most smartphone makers, and that has proved popular for Apple’s M1 chips for Macs. 

Per a report from The Register in May, RISC-V International chief Calista Redmond said a RISC-V laptop would be revealed this year. 

SiFive in March raised $175 million that valued it at $2.5 billion. It’s raised over $350 million to date from investors including Intel Capital, SK Hynix, and Qualcomm Ventures. 

Intel sees some opportunity in RISC-V chips too after last year’s launch of Intel Foundry Services (IFS) and its return to manufacturing chips for others. In February, Intel joined RISC-V as a premier member and, with IFS, announced a $1bn fund to boost tools for ISAs across x86, Arm and RISC-V. And it’s making high-performance RISC-V cores from chip startup Ventana Microcro available through IFS.  

NASA JPL in August announced it had selected US-based industrial embedded control system developer Microchip Technology to develop its HPSC processor. Microchip Technology was contracted to architect, design, and deliver the HPSC processor over three years under a $50 million contract. NASA’s announcement does not mention RISC-V, but Microchip in June announced the industry’s first RISC-V-based SoC Field Programmable Gate Array (FPGA). 

According to Microchip, its design will deliver “comprehensive Ethernet networking, advanced artificial intelligence/machine learning processing and connectivity support” to NASA.  

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